PCF8579 datasheet(16/41 Pages) NXP

16 / 41 page

PCF8579_5

Product data sheet

Rev. 05 — 11 May 2009

16 of 41

NXP Semiconductors

PCF8579

LCD column driver for dot matrix graphic displays

In multiple device applications, the hardware subaddress pins of the PCF8579s (A0 to A3)

are connected to VSS or VDD to represent the desired hardware subaddress code. If two or

more devices share the same slave address, then each device must be allocated a

unique hardware subaddress.

a. Master transmits to slave receiver (write mode)

b. Master reads after sending command string (write commands; read data)

c. Master reads slave immediately after sending slave address (read mode)

Fig 13. I2C-bus protocol

msa830

011110

0 A C

COMMAND

DISPLAY DATA

slave address

acknowledge by

all addressed

PCF8578s / PCF8579s

acknowledge

by A0, A1, A2 and A3

selected PCF8578s /

PCF8579s only

≥ 0 byte(s)

1 byte

update data pointers

and if necessary,

subaddress counter

(a)

msa832

011110

0 A C

COMMAND

slave address

acknowledge by

all addressed

PCF8578s / PCF8579s

≥ 1 byte

(b)

DATA

011110

1 A

slave address

DATA

n bytes

last byte

update data pointers

and if necessary

subaddress counter

acknowledge

from master

no acknowledge

from master

at this moment master

transmitter becomes a

master receiver and

PCF8578/PCF8579 slave

receiver becomes a

slave transmitter

msa831

011110

1 A

DATA

slave address

acknowledge by

all addressed

PCF8578s / PCF8579s

last byte

n bytes

update data pointers

and if necessary,

subaddress counter

(c)

acknowledge

from master

no acknowledge

from master

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