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LT3754

3754f

APPLICATIONS INFORMATION

Example : For a 12W LED driver application requiring 16

strings of 10 LEDs each driven with 20mA, VIN = 24V, fOSC

= 1MHz, Qg (at 7V VGS) = 15nC, I(LEDX) = 20mA, and an

85°C ambient temperature for the LT3754 IC, the LT3754

junction temperature can be approximated as:

TJ = 85°C + [24 • (9.5mA + (16 • 20mA/75) + (1MHz

• 15nC)) + (16 •20mA • 1.1V)] • 34

= 85°C + [(24 • 28.8mA) + (320mA • 1.1V)] • 34

= 85°C + (0.691W + 0.35W) • 34

= 85°C + 35°C

TJ = 120°C

The exposed pad on the bottom of the package must be

soldered to the ground plane. The ground plane should

be connected to an internal copper ground plane with vias

placed directly under the package to spread out the heat

generated by the LT3754.

Circuit Layout Considerations

As with all switching regulators, careful attention must be

given to PCB layout and component placement to achieve

optimal thermal, electrical and noise performance. The

exposed pad of the LT3754 is the only ground connection for

the IC. The exposed pad should be soldered to a continuous

copper ground plane underneath the device to reduce die

temperature and maximize the power capability of the IC.

An analog ground is down bonded to the exposed pad near

the RT and VC pins. ISET, RT and VC components should

be connected to an area of ground copper near these

pins. The OVPSET track should be kept away from fast

moving signals and not loaded with an external capacitor.

GATE pin turn off currents escape through a downbond to

the exposed pad near the GATE pin. This area of copper

should be the power ground (PGND) connection for the

inductor input capacitor, INTVCC capacitor and output

capacitor. A separate bypass capacitor for the VIN pin of

the IC may be required close the VIN pin and connected

to the copper area associated with analog ground. To

minimize MOSFET peak current sensing errors the sense

resistor (RS) should have Kelvin connections to the SENSE

pin and the power ground copper area near the pin. The

MOSFET drain rise and fall times are designed to be as

short as possible for maximum efﬁciency. To reduce the

effects of both radiated and conducted noise, the area of

the copper trace for the MOSFET drain should be kept as

small as possible. Use a ground plane under the switching

regulator to minimize interplane coupling. The Schottky

diode and output capacitor should be placed as close as

possible to the drain node to minimize this high switching

frequency path.

LT3754 Datasheet(PDF) 22 Page - Linear Technology

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