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LTC1967

1967f

100mV to 110mV (+10%) and back (–10%), the step

responses are essentially the same as a standard expo-

nential rise and decay between those two levels. In such

cases, the time constant of the decay will be in between

that of the rising edge and falling edge cases of Figure 10.

Therefore, the worst case is the falling edge response as

it goes to zero, and it can be used as a design guide.

Figure 11 shows the settling accuracy vs settling time for

a variety of averaging capacitor values. If the capacitor

value previously selected (based on error requirements)

gives an acceptable settling time, your design is done.

But with 100

µF, the settling time to even 10% is a full 20

seconds, which is a long time to wait. What can be done

about such a design? If the reason for choosing 100

µF is

to keep the DC error with a 100mHz input less than 0.1%,

the answer is: not much. The settling time to 1% of 32

seconds is just 3.2 cycles of this extremely low frequency.

Averaging very low frequency signals takes a long time.

However, if the reason for choosing 100

µF is to keep the

peak error with a 10Hz input less than 0.1%, there is

another way to achieve that result with a much improved

settling time.

APPLICATIO S I FOR ATIO

TIME (SEC)

100

120

0.05

0.1

0.15

0.2

1967 F10a

0.25

CAVE = 1µF

Figure 10a. LTC1967 Rising Edge with CAVE = 1µF

Figure 10b. LTC1967 Falling Edge with CAVE = 1µF

Figure 11. Settling Time with One Cap Averaging

TIME (SEC)

100

120

0.1

0.2

0.3

0.4

1967 F10b

0.5

CAVE = 1µF

SETTLING TIME (SEC)

0.01

0.1

110

0.1

100

1966 F12

C = 0.1

µF

C = 0.22

µF

C = 0.47

µF C = 1µF

C = 2.2

µF

C = 4.7

µF

C = 10

µF

C = 22

µF

C = 47

µF

C = 100

µF

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