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LTC1967

1967f

APPLICATIO S I FOR ATIO

devoted to sampling, ten time constants elapse. This

allows each sample to settle to within 46ppm and it is these

samples that are used to compute the RMS value.

This is a much higher accuracy than the LTC1967 conver-

sion limits, and far better than the accuracy computed via

the simplistic resistive divider model:

Output Impedance

The LTC1967 output impedance during operation is simi-

larly due to a switched capacitor action. In this case, 20pF

of on-chip capacitance operating at 500kHz translates into

100k

Ω. The closed-loop RMS-to-DC calculation cuts that

in half to the nominal 50k

Ω specified.

In order to create a DC result, a large averaging capacitor

is required. Capacitive loading and time constants are not

an issue on the output.

However, resistive loading is an issue and the 10M

Ω

impedance of a DMM or 10

× scope probe will drag the

output down by –0.5% typ.

During shutdown, the switching action is halted and a

fixed 50k resistor shunts VOUT to OUT RTN so that CAVE is

discharged.

Interfacing with an ADC

The LTC1967 output impedance and the RMS averaging

ripple need to be considered when using an analog-to-

digital converter (ADC) to digitize the LTC1967 RMS

result.

The simplest configuration is to connect the LTC1967

directly to the input of a type 7106/7136 ADC as shown in

Figure 21a. These devices are designed specifically for

DVM/DPM use and include display drivers for a 3 1/2 digit

LCD segmented display. Using a dual-slope conversion,

the input is sampled over a long integration window, which

results in rejection of line frequency ripple when integra-

tion time is an integer number of line cycles. Finally, these

parts have an input impedance in the G

Ω range, with

specified input leakage of 10pA to 20pA. Such a leakage,

combined with the LTC1967 output impedance, results in

just 1

µV to 2µV of additional output offset voltage.

Another type of ADC that has inherent rejection of RMS

averaging ripple is an oversampling

∆Σ ADC such as the

LTC2420. Its input impedance is 6.5M

Ω, but only when it

is sampling. Since this occurs only half the time at most,

if it directly loads the LTC1967, a gain error of –0.32% to

–0.43% results. In fact, the LTC2420 DC input current is

SOURCE

Ω

Ω+

Ω

562

125

–.

This resistive divider calculation does give the correct

model of what voltage is seen at the input terminals by a

parallel load averaged over a several clock cycles, which is

what a large shunt capacitor will do—average the current

spikes over several clock cycles.

When high source impedances are used, care must be taken

to minimize shunt capacitance at the LTC1967 input so as

not to increase the settling time. Shunt capacitance of just

0.8pF will double the input settling time constant and the

error in the above example grows from 46ppm to 0.67%

(6700ppm). As a consequence, it is important to

not try to

filter the input with large input capacitances unless driven

by a low impedance. Keep time constant << 500ns.

When the LTC1967 is driven by op amp outputs, whose

low DC impedance can be compromised by sharp capaci-

tive load switching, a small series resistor may be added.

A 1k resistor will easily settle with the 0.8pF input sampling

capacitor to within 1ppm.

These are important points to consider both during design

and debug. During lab debug, and even production testing,

a high value series resistor to any test point is advisable.

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