Typical Performance Characteristics (Not Guaranteed)

PLL Phase Noise

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The above plot demonstrates the PLL phase noise of the LMX2541SQ3700E operating at 3700 MHz output frequency, phase detector frequency of 100 MHz,

and charge pump gain of 32X. The loop bandwidth was made as wide as possible to fully expose the PLL phase noise and reference source was a 100 MHz

Wenzel crystal. This measurement was done in integer mode. To better understand the impact of using fractional mode, consult the applications section.

The measured noise is the sum of the PLL 1/f noise and noise floor. At offsets below 1 kHz, the PLL 1/f noise is dominates and changes as 10 dB/decade. The

noise at 1 kHz is dominated by this 1/f noise and has a value of -103 dBc/Hz. In the 100 - 200 kHz offset range, the noise is -113.7 dBc/Hz and is dominated by

the PLL noise floor. It can be shown that if the effects of the loop filter peaking and the 1/f noise are subtracted away from this measurement, it would be about

0.6 dB better.

If the phase detector frequency is changed with the VCO frequency held constant, the PLL noise floor will change, but the 1/f noise will remain the same. If the

VCO frequency is changed, both the 1/f noise and PLL noise floor change as 20 dB/decade.

Divider Noise Floor vs. Divider Value Value

(f

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When the divider is engaged (VCO_DIV >0), then the entire system phase noise is reduced by a factor of 20 × log(VCO_DIV). However, the noise floor of the

divider will also add to this noise as is visible at far offsets. Note that the noise floor for Bypass mode is lower because the VCO divider is not engaged.

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