DS3104 datasheet(75/136 Pages) MAXIM

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________________________________________________________________________________________ DS3104-SE

19-4627; Rev 6; 5/09

75 of 136

MCR4

Master Configuration Register 4

35h

Bit #

Name

LKT4T0

—

T4FORCE[3:0]

Default

Bit 7: Lock T4 to T0 (LKT4T0). When this bit is set to 1 (and T0CR1:T4APT0 = 0) all output clocks are generated

from the T0 DPLL, and the T4CR1:T4FREQ field selects the frequency of the T4 APLL. See Section 7.8.2.2. When

LKT4T0 = 0, the T4 APLL can be locked to either the T4 DPLL or the T0 DPLL, depending on the setting of

T0CR1:T4APT0.

0 = T4 APLL can lock to either T4 or the T0 DPLL.

1 = T4 APLL always locked to the T0 DPLL.

Bits 3 to 0: T4 DPL Force Selected Reference (T4FORCE[3:0]). This field provides a way to force a specified

input clock to be the selected reference for the T4 DPLL. Internally this is accomplished by forcing the clock to have

the highest priority (as specified in PTAB1:REF1). Since the T4 DPLL always operates in revertive mode, the

forced clock automatically becomes the selected reference (as specified in PTAB1:SELREF) as well.

When a reference is forced, the activity monitor for that input continues to operate and affect the relevant ISR,

VALSR and MSR register bits. However, when the reference is declared invalid, the T4 DPLL is not allowed to

switch to another input clock. See Section 7.6.3.

0000 = Automatic source selection (normal operation)

0001 = Force to IC1

0010 = Force to IC2

0011 = Force to IC3

0100 = Force to IC4

0101 = Force to IC5

0110 = Force to IC6

0111 = {unused value}

1000 = Force to IC8

1001 = Force to IC9

1010–1110 = {unused value}

1111 = Automatic source selection (normal operation)

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