DS3104 datasheet(49/136 Pages) MAXIM

49 / 136 page

________________________________________________________________________________________ DS3104-SE

19-4627; Rev 6; 5/09

49 of 136

the data on SDO, increment its address counter, and prefetch the following byte. After the address counter reaches

3FFFh, it rolls over to address 0000h and continues to increment.

Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by

pulling

CS high. In response to early terminations, the DS3104-SE resets its SPI interface logic and waits for the

start of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a

data byte, the data byte is not written.

Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the

DS3104-SE is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support

this option, the bus master must not drive the SDI/SDO line when the DS3104-SE is transmitting.

AC Timing. See Table 10-10 and Figure 10-4 for AC timing specifications for the SPI interface.

Figure 7-5. SPI Clock Phase Options

MSB

LSB

SCLK

SDI/SDO

CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES)

CPOL = 0, CPHA = 0

CPOL = 0, CPHA = 1

CPOL = 1, CPHA = 0

CPOL = 1, CPHA = 1

SCLK

DS3104 Datasheet(PDF) 49 Page - Maxim Integrated Products