DS3104 datasheet(21/136 Pages) MAXIM

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________________________________________________________________________________________ DS3104-SE

19-4627; Rev 6; 5/09

21 of 136

7.5

Input Clock Monitoring

Each input clock is continuously monitored for activity. Activity monitoring is described in Sections 7.5.2 and 7.5.3.

The valid/invalid state of each input clock is reported in the corresponding real-time status bit in registers VALSR1

or VALSR2. When the valid/invalid state of a clock changes, the corresponding latched status bit is set in registers

MSR1 or MSR2, and an interrupt request occurs if the corresponding interrupt enable bit is set in registers IER1 or

IER2. Input clocks marked invalid cannot be automatically selected as the reference for either DPLL. If the T4

DPLL does not have any valid input clocks available, the T4NOIN status bit is set to 1 in MSR3.

7.5.1 Frequency Monitoring

The DS3104-SE monitors the frequency of each input clock and invalidates any clock whose frequency is more

than 10,000ppm away from nominal. The frequency range monitor can be disabled by clearing the MCR1.FREN

bit. The frequency range measurement uses the internal 204.8MHz master clock as the frequency reference.

7.5.2 Activity Monitoring

Each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. A leaky bucket

accumulator is similar to an analog integrator: the output amplitude increases in the presence of input events and

gradually decays in the absence of events. When events occur infrequently, the accumulator value decays fully

between events and no alarm is declared. When events occur close enough together, the accumulator increments

faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events

occur infrequently enough, the accumulator can decay faster than it is incremented and eventually reaches the

alarm clear threshold. The leaky bucket events come from the frequency range and fast activity monitors.

The leaky bucket accumulator for each input clock can be assigned one of four configurations (0 to 3) in the

BUCKET field of the

ICR registers. Each leaky bucket configuration has programmable size, alarm declare

threshold, alarm clear threshold, and decay rate, all of which are specified in the LBxy registers.

Activity monitoring is divided into 128ms intervals. The accumulator is incremented once for each 128ms interval in

which the input clock is inactive for more than two cycles (more than four cycles for 155.52MHz, 156.25MHz,

125MHz, 62.5MHz, 25MHz and 10MHz input clocks). Thus, the “fill” rate of the bucket is at most 1 unit per 128ms,

or approximately 8 units/second. During each period of 1, 2, 4, or 8 intervals (programmable), the accumulator

decrements if no irregularities occur. Thus the “leak” rate of the bucket is approximately 8, 4, 2, or 1 units/second.

A leak is prevented when a fill event occurs in the same interval.

When the value of an accumulator reaches the alarm threshold (LBxU register), the corresponding ACT alarm bit is

set to 1 in the

ISR registers, and the clock is marked invalid in the VALSR registers. When the value of an

accumulator reaches the alarm clear threshold (LBxL register), the activity alarm is cleared by clearing the clock’s

ACT bit. The accumulator cannot increment past the size of the bucket specified in the LBxS register. The decay

rate of the accumulator is specified in the LBxD register. The values stored in the leaky bucket configuration

registers must have the following relationship at all times: LBxS ≥ LBxU > LBxL.

When the leaky bucket is empty, the minimum time to declare an activity alarm in seconds is LBxU / 8 (where the x

in LBxU is the leaky bucket configuration number, 0 to 3). The minimum time to clear an activity alarm in seconds is

2^LBxD * (LBxS – LBxL) / 8. As an example, assume LBxU = 8, LBxL = 1, LBxS = 10, and LBxD = 0. The minimum

time to declare an activity alarm would be 8 / 8 = 1 second. The minimum time to clear the activity alarm would be

2^0 * (10 – 1) / 8 = 1.125 seconds.

7.5.3 Selected Reference Activity Monitoring

The input clock that each DPLL is currently locked to is called the selected reference. The quality of a DPLL’s

selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference

can cause unwanted jitter, wander, or frequency offset on the output clocks. When anomalies occur on the selected

reference they must be detected as soon as possible to give the DPLL opportunity to temporarily disconnect from

the reference until the reference is available again. By design, the regular input clock activity monitor (Section

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