SA53

6

SA53U

P r o d u c t I n n o v a t i o n F r o m

TABLE.PINDESCRIPTIONS

Pin#

PinName

SignalType

Simplified Pin Description

5,9,11,13

SGND

Power

Analog and digital GND – internally connected to PGND

15

1b

Logic Input

Logic high commands 1 phase lower FET to turn on

17

1t

Logic Input

Logic high commands 1 phase upper FET to turn on

19

V

DD

Power

Logic Supply (5V)

21

I1

Analog Output

Phase 1 current sense output

23

DIS2

Logic Input

Logic high places all outputs in a high impedance state

25

TEMP

Logic Output

Thermal indication of die temperature above 135ºC

46,47,48,49 V

Power

High Voltage Supply phase 2

33,34,35

OUT 1

Power Output

Half Bridge 1 Power Output

37,38,39,40 PGND (phase 1)

Power

High Current GND Return Path for Power Outputs 1&2

26,27,58,59 HS

Mechanical

Pins connected to the package heat slug

2,4,6,8,10,

12,14,16,18,

20,22,24,28,

32,36,41,42,

43,44,45,50,

54,60,62,64

NC

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Do Not Connect

.2PinDescriptions

V

quency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as

close to the V

current peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional

discussion regarding bypass capacitor selection. Note that V

Pins 46-49 carry supply current for phase 2. Phase 1 may be operated at a different supply voltage from phase

2. Both V

OUT,OUT2:These pins are the power output connections to the load. NOTE: When driving an inductive load, it

is recommended that two Schottky diodes with good switching characteristics (fast t

each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)

PgND:Power Ground. This is the ground return connection for the output FETs. Return current from the load flows

through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section

2.1 of this datasheet for more details.

SC:Short Circuit output. If a condition is detected on any output which is not in accordance with the input com-

mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approxi-

mately 200ns during switching transitions but in high current applications, short glitches may appear on the

SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal

12kΩ series resistor.

b,2b:These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower N-

channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low

side N-channel FET off. If 2b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection

circuitry will turn off both FETs in order to prevent shoot-through on that output phase. Protection circuitry also

includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of

the top and bottom input signals.

t,2t:These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper P-

channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-

channel FET off.