SA303

6

SA303U

P r o d u c t I n n o v a t i o n F r o m

Pin#

PinName

SignalType

Simplified Pin Description

9

SGND

Power

Analog and digital GND – internally connected to PGND

11

Bt

Logic Input

Logic high commands B phase upper FET to turn on

13

Bb

Logic Input

Logic high commands B phase lower FET to turn on

15

Ab

Logic Input

Logic high commands A phase lower FET to turn on

17

At

Logic Input

Logic high commands A phase upper FET to turn on

19

V

DD

Power

Logic Supply (5V)

21

Ia

Analog Output

Phase A current sense output

23

DIS2

Logic Input

Logic high places all outputs in a high impedance state

25

TEMP

Logic Output

Thermal indication of die temperature above 135ºC

42,43,44

OUT B

Power Output

Half bridge b Power Output

46,47,48,49 V

Power

High Voltage Supply phase b&C

33,34,35

OUT A

Power Output

Half bridge A Power Output

37,38,39,40 PGND (phase A&b) Power

High Current GND Return Path for Power Outputs A&b

26,27,58,59 HS

Mechanical

Pins connected to the package heat slug

2,4,6,8,10,

12,14,16,18,

20,22,24,28,

32,36,41,45,

50,54,60,62,

64

NC

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Do Not Connect

.2PinDescriptions

V

cy characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to

the V

rent peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional

discussion regarding bypass capacitor selection. Note that V

Pins 46-49 carry supply current for phases b & C. Phase A may be operated at a different supply voltage from

phases B & C. Both V

OUTA,OUTB,OUTC: These pins are the power output connections to the load. NOTE: When driving an induc-

tive load, it is recommended that two Schottky diodes with good switching characteristics (fast t

connected to each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See

Section 2.6)

PgND:Power Ground. This is the ground return connection for the output FETs. Return current from the load flows

through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section

2.1 of this datasheet for more details.

SC:Short Circuit output. If a condition is detected on any output which is not in accordance with the input com-

mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approxi-

mately 200ns during switching transitions but in high current applications, short glitches may appear on the

SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal

12kΩ series resistor.

Ab,Bb,Cb:These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower

N-channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low

side N-channel FET off. If Ab, bb, or Cb is high at the same time that a corresponding At, bt, or Ct input is high,

protection circuitry will turn off both FETs in order to prevent shoot-through on that output phase. Protection

circuitry also includes a dead-time generator, which inserts dead time in the outputs in the case of simultane-

ous switching of the top and bottom input signals.

TABLE.PINDESCRIPTIONS-Cont.