AD5291 datasheet(7/28 Pages) AD

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AD5291/AD5292

Rev. 0 | Page 7 of 28

INTERFACE TIMING SPECIFICATIONS

VDD/VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, −40°C < TA < + 105°C. All specifications TMIN to TMAX, unless otherwise noted.

Table 5.

Parameter

Limit1

Unit

Description

t12

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC to SCLK falling edge setup time

ns min

Data setup time

ns min

Data hold time

ns min

SCLK falling edge to SYNC rising edge

4003

ns min

Minimum SYNC high time

ns min

SYNC rising edge to next SCLK fall ignore

t104

ns min

RDY rising edge to SYNC falling edge

t114

ns max

SYNC rising edge to RDY fall time

t124

2.4

μs max

RDY low time, RDAC register write command execute time (R-Perf mode)

t124

410

ns max

RDY low time, RDAC register write command execute time (normal mode)

t124

ms max

RDY low time, memory program execute time

t124

1.5

ms min

Software\hardware reset

t134

450

ns max

RDY low time, RDAC register readback execute time

t134

1.3

ms max

RDY low time, memory readback execute time

t144

450

ns max

SCLK rising edge to SDO valid

tRESET

ns min

Minimum RESET pulse width (asynchronous)

tPOWER-UP5

ms max

Power-on OTP restore time

1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2 Maximum SCLK frequency is 50 MHz.

3 Refer to t12 and t13 for RDAC register and memory commands operations.

4 RPULL_UP = 2.2 kΩ to VLOGIC, with a capacitance load of 168 pF.

5 Typical power supply voltage slew rate of 2 ms/V.

DATA BITS

DB9 (MSB)

DB0 (LSB)

CONTROL BITS

Figure 2. AD5291/AD5292 Shift Register Content

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