AD7192 datasheet(7/40 Pages) AD

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AD7192

Rev. A | Page 7 of 40

TIMING CHARACTERISTICS

AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter

Limit at TMIN, TMAX (B Version)

Unit

Conditions/Comments1, 2

100

ns min

SCLK high pulse width

100

ns min

SCLK low pulse width

READ OPERATION

ns min

CS falling edge to DOUT/RDY active time

ns max

DVDD = 4.75 V to 5.25 V

ns max

DVDD = 2.7 V to 3.6 V

t23

ns min

SCLK active edge to data valid delay4

ns max

DVDD = 4.75 V to 5.25 V

ns max

DVDD = 2.7 V to 3.6 V

t55, 6

ns min

Bus relinquish time after CS inactive edge

ns max

ns min

SCLK inactive edge to CS inactive edge

ns min

SCLK inactive edge to DOUT/RDY high

WRITE OPERATION

ns min

CS falling edge to SCLK active edge setup time4

ns min

Data valid to SCLK edge setup time

t10

ns min

Data valid to SCLK edge hold time

t11

ns min

CS rising edge to SCLK edge hold time

1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2 See Figure 3 and Figure 4.

3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4 The SCLK active edge is the falling edge of SCLK.

5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY

is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the

digital word can be read only once.

CIRCUIT AND TIMING DIAGRAMS

ISINK (1.6mA WITH DVDD = 5V,

100µA WITH DVDD = 3V)

ISOURCE (200µA WITH DVDD = 5V,

100µA WITH DVDD = 3V)

1.6V

OUTPUT

50pF

Figure 2. Load Circuit for Timing Characterization

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