AD7192

Rev. A | Page 21 of 40

Table 18. Operating Modes

MD2

MD1

MD0

Mode

0

0

0

Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs

conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go

low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the commun-

ications register to 1, which enables continuous read. When continuous read is enabled, the conversions are

automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to

output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of

the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent

conversions are available at the selected output data rate, which is dependent on filter choice.

0

0

1

Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single

conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then

performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in

the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data

register until another conversion is performed. RDY remains active (low) until the data is read or another conversion

is performed.

0

1

0

Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are

still provided.

0

1

1

Power-down mode. In power-down mode, all AD7192 circuitry, except the bridge power-down switch, is powered

down. The bridge power-down switch remains active because the user may need to power up the sensor prior to

powering up the AD7192 for settling reasons. The external crystal, if selected, remains active.

1

0

0

Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the

calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a

calibration. The measured offset coefficient is placed in the offset register of the selected channel.

1

0

1

Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration.

RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed

in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the

selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-

calibration.

1

1

0

System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as

selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and

returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured

offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required

each time the gain of a channel is changed.

1

1

1

System full-scale calibration. The user should connect the system full-scale input to the channel input pins as

selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and

returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured

full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required

each time the gain of a channel is changed.

CONFIGURATION REGISTER

(RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117)

The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to

configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the

gain, and to select the analog input channel.

Table 19 outlines the bit designations for the filter register. CON0 through CON23 indicate the bit locations. CON denotes that the bits

are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset

default status of that bit.

CON23

CON22

CON21

CON20

CON19

CON18

CON17

CON16

CHOP(0)

0(0)

0(0)

REFSEL(0)

0(0)

0(0)

0(0)

(0)

CON15

CON14

CON13

CON12

CON11

CON10

CON9

CON8

CH7(0)

CH6(0)

CH5(0)

CH4(0)

CH3(0)

CH2(0)

CH1(0)

CH0(1)

CON7

CON6

CON5

CON4

CON3

CON2

CON1

CON0

BURN(0)

REFDET(0)

0(0)

BUF(1)

U/B (0)

G2(1)

G1(1)

G0(1)