AD7193 datasheet(39/56 Pages) AD

39 / 56 page

AD7193

Rev. A | Page 39 of 56

When the analog input is constant or a channel change occurs,

valid conversions are available at a constant output data rate.

When conversions are being performed on a single channel and

a step change occurs on the analog input, the ADC continues to

output fully settled conversions if the step change is synchronized

with the conversion process. If the step change is asynchronous,

one conversion is output from the ADC, which is not completely

settled (see Figure 30).

ANALOG

INPUT

ADC

OUTPUT

FULLY

SETTLED

fADC

Figure 30. Sinc4 Zero Latency Operation

Table 28 shows examples of output data rate and the corres-

ponding FS values.

Table 28. Examples of Output Data Rates and the

Corresponding Settling Time (Zero Latency)

FS[9:0]

Output Data Rate

Settling Time

480

2.5 Hz

400 ms

12.5 Hz

80 ms

15 Hz

66.6 ms

Sinc4 50 Hz/60 Hz Rejection

Figure 31 shows the frequency response of the sinc4 filter when

FS[9:0] is set to 96 and the master clock is 4.92 MHz. With zero

latency disabled, the output data rate is equal to 50 Hz. With

zero latency enabled, the output data rate is 12.5 Hz. The sinc4

filter provides 50 Hz (±1 Hz) rejection in excess of 120 dB

minimum, assuming a stable master clock.

–120

–110

100

125

150

FREQUENCY (Hz)

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

Figure 31. Sinc4 Filter Response (FS[9:0] = 96)

Figure 32 shows the frequency response when FS[9:0] is

programmed to 80 and the master clock is equal to 4.92 MHz.

The output data rate is 60 Hz when zero latency is disabled and

15 Hz when zero latency is enabled. The sinc4 filter provides

60 Hz (±1 Hz) rejection of 120 dB minimum, assuming a stable

master clock.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

150

FREQUENCY (Hz)

Figure 32. Sinc4 Filter Response (FS[9:0] = 80)

Simultaneous 50 Hz and 60 Hz rejection is obtained when

FS[9:0] is programmed to 480 and the master clock equals

4.92 MHz. The output data rate is 10 Hz when zero latency is

disabled and 2.5 Hz when zero latency is enabled. The sinc4

filter provides 50 Hz (±1 Hz) and 60 Hz (±1 Hz) rejection of

120 dB minimum, assuming a stable master clock.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

150

FREQUENCY (Hz)

Figure 33. Sinc4 Filter Response (FS[9:0] = 480)

Simultaneous 50 Hz/60 Hz rejection can also be achieved using

the REJ60 bit in the mode register. When FS[9:0] is set to 96

and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz.

AD7193 Datasheet(PDF) 39 Page - Analog Devices

AD7193 Datasheet(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL