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AD7193 Datasheet(PDF) 49 Page - Analog Devices

Part # AD7193
Description  4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
PDF  56 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7193 Datasheet(HTML) 49 Page - Analog Devices

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AD7193
Rev. A | Page 49 of 56
FAST SETTLING MODE (CHOP ENABLED)
Chop can be enabled in the fast settling mode. With chop
enabled, the ADC offset and offset drift are minimized. The
analog input pins are continuously swapped. With the analog
input pins connected in one direction, the settling time of the
sinc filter is allowed and a conversion is recorded. The analog
input pins are then inverted, and another settled conversion is
obtained. Subsequent conversions are averaged so that the offset
is minimized. This continuous swapping of the analog input
pins and the averaging of subsequent conversions means that
the offset drift is also minimized.
Chopping does not change the output data rate. However, the
settling time equals
tSETTLE = 2/fADC
Consequently, if chop is enabled, the sinc4 filter is selected, FS[9:0]
is set to 6 and averaging by 16 is enabled, and the output data
rate is equal to 42.1 Hz. Therefore, the conversion time equals
1/42.10 Hz or 23.75 ms and the settling time is equal to 47.5 ms.



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