XRT86VL30 datasheet(27/62 Pages) EXAR

27 / 62 page

XRT86VL30

REV. 1.0.3

T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL

RxCHCLK

n/a

Receive Channel Clock Output (RxCHCLK):

The exact function of this pin depends on whether or not the

receive framer enables the receive fractional/signaling inter-

face to output fractional data, as described below.

If receive fractional/signaling interface is disabled:

This pin indicates the boundary of each time slot of an

inbound DS1/E1 frame. In T1 mode, this output pin is a

192kHz clock which pulses "High" during the LSB of each 24

time slots. In E1 mode, this output pin is a 256kHz clock

which pulses "High" during the LSB of each 32 time slots.

System Equipment can use this clock signal to sample the

RxCHN0 through RxCHN4 time slot identifier pins to deter-

mine which time slot is being output.

If receive fractional/signaling interface is enabled:

RxCHCLK is the fractional interface clock which either out-

puts a clock signal for the time slot that has been configured

to output fractional data, or outputs an enable signal for the

fractional time slot so that fractional data can be clocked out

of the device using the RxSERCLK pin.

NOTE:

Receive fractional interface can be enabled by

programming to bit 4 - RxFr1544/RxFr2048 bit from

RECEIVE SYSTEM SIDE INTERFACE

SIGNAL NAME

128-PIN#

80-PIN#

TYPE

OUTPUT

DRIVE (MA)

DESCRIPTION

XRT86VL30 Datasheet(PDF) 27 Page - Exar Corporation