XRT86VL30 datasheet(32/62 Pages) EXAR

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XRT86VL30

T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL

REV. 1.0.3

REQ0

DMA Cycle Request Output—DMA Controller 0 (Write):

This output pin is used to indicate that DMA transfers (Write) are requested

by the T1/E1 Framer.

On the transmit side (i.e., To transmit data from external DMA controller to

HDLC buffers within the XRT86VL30), DMA transfers are only requested

when the transmit buffer status bits indicate that there is space for a com-

plete message or cell.

The DMA Write cycle starts by T1/E1 Framer asserting the DMA Request

(REQ0) ‘low’, then the external DMA controller should drive the DMA

Acknowledge (ACK0) ‘low’ to indicate that it is ready to start the transfer.

The external DMA controller should place new data on the Microprocessor

data bus each time the Write Signal is Strobed low if the WR is configured

as a Write Strobe. If WR is configured as a direction signal, then the exter-

nal DMA controller would place new data on the Microprocessor data bus

each time the Read Signal (RD) is Strobed low.

The Framer asserts this output pin (toggles it "Low") when at least one of

the Transmit HDLC buffers are empty and can receive one more HDLC

message.

The Framer negates this output pin (toggles it “High”) when the HDLC

buffer can no longer receive another HDLC message.

REQ1

DMA Cycle Request Output—DMA Controller 1 (Read):

This output pin is used to indicate that DMA transfers (Read) are requested

by the T1/E1 Framer.

On the receive side (i.e., To transmit data from HDLC buffers within the

XRT86VL30 to external DMA Controller), DMA transfers are only requested

when the receive buffer contains a complete message or cell.

The DMA Read cycle starts by T1/E1 Framer asserting the DMA Request

(REQ1) ‘low’, then the external DMA controller should drive the DMA

Acknowledge (ACK1) ‘low’ to indicate that it is ready to receive the data.

The T1/E1 Framer should place new data on the Microprocessor data bus

each time the Read Signal is Strobed low if the RD is configured as a Read

Strobe. If RD is configured as a direction signal, then the T1/E1 Framer

would place new data on the Microprocessor data bus each time the Write

Signal (WR) is Strobed low.

The Framer asserts this output pin (toggles it "Low") when one of the

Receive HDLC buffer contains a complete HDLC message that needs to be

read by the µC/µP.

The Framer negates this output pin (toggles it “High”) when the Receive

HDLC buffers are depleted.

INT

Interrupt Request Output:

This active-low output signal will be asserted when the XRT86VL30 device

is requesting interrupt service from the Microprocessor. This output pin

should typically be connected to the “Interrupt Request” input of the Micro-

processor.

The Framer will assert this active "Low" output (toggles it "Low"), to the local

µP, anytime it requires interrupt service.

MICROPROCESSOR INTERFACE

SIGNAL NAME

128-PIN#

80-PIN#

TYPE

DESCRIPTION

XRT86VL30 Datasheet(PDF) 32 Page - Exar Corporation

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