XRT86VL30 datasheet(34/62 Pages) EXAR

34 / 62 page

XRT86VL30

T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL

REV. 1.0.3

RDY

Ready/Data Transfer Acknowledge Output:

The exact behavior of this pin depends upon the type of Microprocessor/

Microcontroller the XRT86VL30 has been configured to operate in, as

defined by the PTYPE[2:0] pins.

Intel Asynchronous Mode - RDY* - Ready Output

Tis output pin will function as the “active-low” READY output.

During a READ or WRITE cycle, the Microprocessor Interface block will

toggle this output pin to the logic low level, ONLY when the Microprocessor

Interface is ready to complete or terminate the current READ or WRITE

cycle. Once the Microprocessor has determined that this input pin has tog-

gled to the logic “low” level, then it is now safe for it to move on and execute

the next READ or WRITE cycle.

If (during a READ or WRITE cycle) the Microprocessor Interface block is

holding this output pin at a logic “high” level, then the Microprocessor is

expected to extend this READ or WRITE cycle, until it detects this output

pin being toggled to the logic low level.

Motorola Asynchronous Mode - DTACK* - Data Transfer Acknowledge

Output

Tis output pin will function as the “active-low” DTACK output.

During a READ or WRITE cycle, the Microprocessor Interface block will

toggle this output pin to the logic low level, ONLY when the Microprocessor

Interface is ready to complete or terminate the current READ or WRITE

cycle. Once the Microprocessor has determined that this input pin has tog-

gled to the logic “low” level, then it is now safe for it to move on and execute

the next READ or WRITE cycle.

If (during a READ or WRITE cycle) the Microprocessor Interface block is

holding this output pin at a logic “high” level, then the Microprocessor is

expected to extend this READ or WRITE cycle, until it detects this output

pin being toggled to the logic low level.

Power PC 403 Mode - RDY Ready Output:

This output pin will function as the “active-high” READY output.

During a READ or WRITE cycle, the Microprocessor Interface block will

toggle this output pin to the logic high level, ONLY when the Microproces-

sor Interface is ready to complete or terminate the current READ or WRITE

cycle. Once the Microprocessor has sampled this signal being at the logic

“high” level upon the rising edge of PCLK, then it is now safe for it to move

on and execute the next READ or WRITE cycle.

If (during a READ or WRITE cycle) the Microprocessor Interface block is

holding this output pin at a logic “low” level, then the Microprocessor is

expected to extend this READ or WRITE cycle, until it samples this output

pin being at the logic low level.

NOTE: The Microprocessor Interface will update the state of this output pin

upon the rising edge of PCLK.

MICROPROCESSOR INTERFACE

SIGNAL NAME

128-PIN#

80-PIN#

TYPE

DESCRIPTION

XRT86VL30 Datasheet(PDF) 34 Page - Exar Corporation

XRT86VL30 Datasheet(HTML) 34 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL