56F8366 datasheet(112/182 Pages) FREESCALE

112 / 182 page

56F8366 Technical Data, Rev. 7

112

Freescale Semiconductor

Preliminary

5.6.30.5 Reserved—Bit 4

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.6.30.6 IRQB State Pin (IRQB STATE)—Bit 3

This read-only bit reflects the state of the external IRQB pin.

5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2

This read-only bit reflects the state of the external IRQA pin.

5.6.30.8 IRQB Edge Pin (IRQB Edg)—Bit 1

This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and Wait

modes, it is automatically level-sensitive.

•0 = IRQB interrupt is a low-level sensitive (default)

•1 = IRQB interrupt is falling-edge sensitive

5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0

This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait

modes, it is automatically level -ensitive.

•0 = IRQA interrupt is a low-level sensitive (default)

•1 = IRQA interrupt is falling-edge sensitive

5.6.31 Reserved—Base + $1E

5.6.32 Interrupt Priority Register 10 (IPR10)

Note: This register is NOT available in the 56F8166 device.

5.6.32.1 Reserved—Bits 15–8

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

Base + $1F

12 11 10

Read

FLECAN2_

MSGBUF IPL

FLECAN2_

WKUP IPL

FLECAN2_

ERR IPL

FLECAN2_

BOFF IPL

Write

RESET

0000

56F8366 Datasheet(PDF) 112 Page - Freescale Semiconductor, Inc