56F8366 datasheet(115/182 Pages) FREESCALE

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Features

56F8366 Technical Data, Rev. 7

Freescale Semiconductor

115

Preliminary

6.2 Features

The SIM has the following features:

•

Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory

•

Power-saving clock gating for peripheral

•

Three power modes (Run, Wait, Stop) to control power utilization

— Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation

— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be

explicitly done

— Wait mode shuts down the 56800E core and unnecessary system clock operation

— Run mode supports full part operation

•

Controls to enable/disable the 56800E core WAIT and STOP instructions

•

Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will be either

3 x 32 clocks (phased release of reset) for reset, except for POR, which is 221 clock cycles.

•

Controls reset sequencing after reset

•

Software-initiated reset

•

Four 16-bit registers reset only by a Power-On Reset usable for general purpose software control

•

System Control Register

•

Registers for software access to the JTAG ID of the chip

6.3 Operating Modes

Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the

various chip operating modes and take appropriate action. These are:

•

Reset Mode, which has two submodes:

— POR and RESET operation

The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the

RESET pin is asserted.

— COP reset and software reset operation

The 56800E core and all peripherals are reset. The MA bit within the OMR is not changed. This allows

the software to determine the boot mode (internal or external boot) to be used on the next reset.

•

Run Mode

This is the primary mode of operation for this device. In this mode, the 56800E controls chip operation.

•

Debug Mode

The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and

PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor

from being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details.

•

Wait Mode

In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.

Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other

peripherals continue to run.

56F8366 Datasheet(PDF) 115 Page - Freescale Semiconductor, Inc

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