ICS840271I

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

9

ICS840271BGI REV. A APRIL 23, 2009

Schematic Example

Figure 4 shows an example of ICS840271I applications schematic.

driven by either a 3.3V LVPECL or LVDS driver. One example of

LVCMOS termination is shown in this schematic. The decoupling

capacitors should be located a close as possible to the power pin.

Figure 4. ICS840271I Schematic layout

VDD

U1

1

2

3

4

8

7

6

5

VDDA

SEL0

CLK

nCLK

VDD

Q

GND

SEL1

nCLK

R3

125

VDD

SEL1

R1

10

Logic Input Pin Examples

RD1

Not Install

Q

RU2

Not Install

C3

10u

R2

33

Set Logic

Input to

'1'

Set Logic

Input to

'0'

VDDA

VDD

Zo = 50

R4

125

LVPECL Driv er

C2

0.1u

Zo = 50

CLK

C1

0.01u

R6

84

R5

84

LVCMOS

VDD

RU1

1K

To Logic

Input

pins

VDD

SEL0

RD2

1K

To Logic

Input

pins

Zo = 50 Ohm