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ICS840271I Datasheet(PDF) 1 Page - Integrated Device Technology |
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ICS840271I Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 13 page ![]() SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR ICS840271I IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 1 ICS840271BGI REV. A APRIL 23, 2009 General Description The ICS840271I is a PLL-based Frequency Translator intended for use in telecommunication applications such as Synchronous Ethernet. The internal PLL translates Ethernet clock frequencies such as 125MHz (1Gb Ethernet), 156.25MHz (10GbE XAUI) and 161.1328MHz (10Gb Ethernet) to an output frequency of 25MHz. The PLL does not any require external components. The input frequency is selectable by a 2-pin interface. The ICS840271I is optimized for low cycle-to-cycle jitter on the 25MHz output signal. The input of the device accepts differential (LVPECL, LVDS, LVHSTL, SSTL, HCSL) or single-ended (LVCMOS) signals. The extended temperature range supports telecommunication and networking equipment requirements. The ICS840271I uses a small RoHS 6, 8-pin TSSOP package and is an effective solution for space-constrained applications. Features • Clock frequency translator for Synchronous Ethernet applications • One single-ended output (LVCMOS or LVTTL levels), 16 Ω output impedance • Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels • Supports input clock frequencies of: 125MHz, 156.25MHz or 161.1328MHz • Generates a 25MHz output clock signal • Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/LVTTL) input levels • Internal PLL is optimized for low cycle-to-cycle jitter at the output • Full 3.3V or 2.5V supply voltage • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package HiPerClockS™ ICS ICS840271I 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View Pin Assignment 1 2 3 4 8 7 6 5 VDDA nCLK CLK SEL0 GND Q SEL1 VDD 25 MHz Q SEL(1:0) Input Control Logic CLK nCLK 00 = PLL Bypass 01 = 161.1328125MHz 10 = 156.2500000MHz 11 = 125.0000000MHz PLL Pre- divider Output divider Feedback divider Block Diagram |
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