TLE8262E datasheet(40/93 Pages) INFINEON

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Data Sheet

Rev. 1.0, 2009-03-31

TLE8262E

WK Pin

9WK Pin

9.1

Block Description

Figure 16

Functional Block Diagram

The internal voltage regulator (

cc1µC) and the entire SBC can wake up by changing the wake input voltage. The

WK input pin is a bi-level sensitive input. This means that both transitions, HIGH to LOW and LOW to HIGH, result

in a wake-up. The filtering time is

WK, f.The wake-up capability can be enabled or disabled via SPI command. In

case of reverse polarity, no special protection must be set if the absolute maximum rating is respected. When the

SBC is below the minimum

UVOFF, (SBC OFF Mode) the pin WK is at high impedance; a wake event will be

ignored.

The state of the WK pin (low or high) can always be read in Normal Mode, Stop Mode and SW Flash Mode at the

bit WK State. When setting the bit “WK PIN on/off” to 1, the device wakes up from Sleep Mode with a high to low

or low to high transition. From Fail-Safe Mode the device will always go to Restart Mode with a high to low or low

to high transition. If the bit “WK PIN on/off” is set to 1 in Normal, Stop or SBC SW Flash Mode the interrupt bits

“WK 0 WK pin” and/or “WK 1 WK pin” are set in case of a change on the WK pin and an interrupt is generated if

not masked. With the bits “WK 0 WK pin” and “WK 1 WK pin” the interrupt for low to high transition and high to low

transition can be masked separately.

9.2

Wake-Up Timing

Figure 17 shows typical wake-up timing and parasitic filtering. The filtering time is

WK, f.. This is used to avoid a

parasitic wake-up due to EMC disturbances. Specifically, the voltage transition on pin WK must be higher than the

WK,TH and longer than tWK,f to be understood as a wake-up signal.

Internal supply

IPU_MON

Wake.vsd

IPD_MON

IWK

State

machine

TLE8262E Datasheet(PDF) 40 Page - Infineon Technologies AG