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MIC22700 Datasheet(PDF) 2 Page - Micrel Semiconductor |
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MIC22700 Datasheet(HTML) 2 Page - Micrel Semiconductor |
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2 / 21 page ![]() Micrel, Inc. MIC22700 July 2009 2 M9999-072209-B Ordering Information Part Number Voltage Junction Temp. Range Package Lead Finish MIC22700YML Adj. –40° to +125°C 24-Pin 4x4 MLF ® Pb-Free Note: MLF ® is a GREEN RoHS compliant package. Lead finish is NiPdAu. Mold compound is Halogen Free. Pin Configuration PVIN EN DELAY RC POR/PG PVIN PVIN SVIN SGND COMP FB PVIN EP 24-Pin 4mm x 4mm MLF ® (ML) Pin Description Pin Number Pin Name Description 1, 6, 13, 18 PVIN Power Supply Voltage (Input): Requires bypass capacitor to GND. 17 SVIN Signal Power Supply Voltage (Input): Requires bypass capacitor-to-GND. 2 EN Enable/Delay (Input): When this pin is pulled higher than the enable threshold, the part will start up. Below this voltage the device is in its low quiescent current mode. The pin has a 1µA current source charging it to VIN. By adding a capacitor to this pin a delay may easily be generated. The enable function will not operate with an input voltage lower than the min specified. 4 RC Ramp Control: Capacitor to ground from this pin determines slew rate of output voltage during start-up. This can be used for tracking capability as well as soft start. 14 FB Feedback: Input to the error amplifier, connect to the external resistor divider network to set the output voltage. 15 COMP Compensation pin (Input): Place a RC to GND to compensate the device, see applications section. 5 POR/PG Power On Reset (Output): Open-drain output device indicates when the output is out of regulation and is active after the delay set by the delay pin. 7, 12, 19, 24 PGND Power Ground: Ground 16 SGND Signal Ground: Ground 3 DELAY Delay (Input): Capacitor to ground sets internal delay timer. Timer delays power- on reset (POR) output at turn-on and ramp down at turn-off. 8, 9, 10, 11, 20, 21, 22, 23 SW Switch (Output): Internal power MOSFET output switches. EP GND Exposed Pad (Power): Must make a full connection to a GND plane for full output power to be realized. |
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