SCA8X0 datasheet(32/35 Pages) VTI

32 / 35 page

SCA8X0/21X0/3100 Series

VTI Technologies Oy

32/35

www.vti.fi

Doc. Nr. 82 694 00 C

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Specified operation voltage (VDD) range 3.05...3.6 V

To achieve high EMC DPI performance, add serial inductance (L1) to VDD line

before serial resistance (for example Murata: BLM18HG102S)

Figure 9:

Recommended circuit diagram

6.6

Recommended PWB layout

Recommended PWB layout for all product family components with SPI interface is shown in Figure

10 and Figure 11. Following design rules and recommendations should be considered:

Required:

Connect (C4) 100 nF SMD capacitor between AVDD and AVSS right next to

component pins AVDD and AVSS

Connect (C5) 100 nF SMD capacitor between DVDD and DVSS right next to

component pins DVDD and DVSS

Use separate ground levels AVSS and DVSS under and near the component

but connect them together on the PCB, see Figure 10

Locate ground plate under component

Do not route signals or power supplies under the component on top layer

Ensure good ground connection of Egnd (pin12) to AVSS

Recommended:

Locate digital ground under digital signal lines

Do not route digital signals one upon the other for long distance

Avoid crossing of AVDD path with digital signal especially between serial

resistance R1 and AVDD pin

10 Do not route digital signals under the component on 2nd layer

MISO

CSB

AVSS

AVDD

CSB

MISO

DVSS

DVDD

EGND

PWM

MOSI

SCK

SCA8x0

SCA21x0

SCA3100

SCK

MOSI

100 nF

10 µF

10 Ω

VDD

Note 1

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