SCA8X0/21X0/3100 Series

VTI Technologies Oy

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www.vti.fi

Doc. Nr. 82 694 00 C

C

LSB

k

LSB

Temp

C

C

Temp

dec

°

−

+

°

±

=

°

512

10

23

,

TEMP_LSB registers in decimal format, bits(t9:0). k is temperature slope factor specified as

Min

Typ

Max

Unit

k

2.8

3.2

3.6

LSB/

3.1.6

Status Register (STATUS)

Address: 2h

Bits

Mode

Initial

Value

Name

Description

7:3

-

-

Reserved

2

R

0

ATEST

Analog test mode status

1 – Test mode is active

0 – Test mode is not active

1

R

0

CSMERR

EEPROM Checksum Error. In

SCA21X0/SCA31X0 ST bit of SPI frame is also

set if CSMERR is set.

0

R

0

FRME

SPI frame error. Bit is reset, when next correct

SPI frame is received. Bit is also visible in SPI

frame.

3.1.7

Interrupt Status Register (INT_STATUS)

Address: 16h

Bits

Mode

Initial

Value

Name

Description

7

R

0

Reserved

6

R

0

SAT

Saturation status of output data

1 – Over range detected, one or 2-3 of xyz axis is

saturated and output data is not valid.

0 – Data in range

SAT bit is also visible in SPI frame. This bit can be

active after start-up or reset stage before signal

path settles to final value and it has to be

acknowledged in start-up sequence (see Table 3)

or after SW reset or after PORST stage.

5

R

0

STS

Status of gravitation based start-up self test

1 – Failure

0 – No failure

STS sets also ST bit in SPI frame.

4

R

0

STC

Status of continuous self test

1 – Failure

0 – No failure

STC sets also ST bit in SPI frame.

3:0

R

0000

Reserved

The bits in this interrupt status register and corresponding SPI frame bits are cleared after register

has been read. Register reading is treated as interrupt acknowledgement signal. These bits are

kept active even failure condition is over if they are not acknowledged.

This register is not defined in SCA8X0.