AT32AP7002 datasheet(13/896 Pages) ATMEL

13 / 896 page

32054F–AVR32–09/09

AT32AP7002

4.0.1

AVR32AP CPU

• 32-bit load/store AVR32B RISC architecture.

– Up to 15 general-purpose 32-bit registers.

– 32-bit Stack Pointer, Program Counter and Link Register reside in register file.

– Fully orthogonal instruction set.

– Privileged and unprivileged modes enabling efficient and secure Operating Systems.

– Innovative instruction set together with variable instruction length ensuring industry leading

code density.

– DSP extention with saturating arithmetic, and a wide variety of multiply instructions.

– SIMD extention for media applications.

• 7 stage pipeline allows one instruction per clock cycle for most instructions.

– Java Hardware Acceleration.

– Byte, half-word, word and double word memory access.

– Unaligned memory access.

– Shadowed interrupt context for INT3 and multiple interrupt priority levels.

– Dynamic branch prediction and return address stack for fast change-of-flow.

– Coprocessor interface.

• Full MMU allows for operating systems with memory protection.

• 16Kbyte Instruction and 16Kbyte data caches.

– Virtually indexed, physically tagged.

– 4-way associative.

– Write-through or write-back.

• Nexus Class 3 On-Chip Debug system.

– Low-cost NanoTrace supported.

4.0.2

Pixel Coprocessor (PICO)

• Coprocessor coupled to the AVR32 CPU Core through the TCB Bus.

– Coprocessor number one on the TCB bus.

• Three parallel Vector Multiplication Units (VMU) where each unit can:

– Multiply three pixel components with three coefficients.

– Add the products from the multiplications together.

– Accumulate the result or add an offset to the sum of the products.

• Can be used for accelerating:

– Image Color Space Conversion.

•Configurable Conversion Coefficients.

• Supports packed and planar input and output formats.

• Supports subsampled input color spaces (i.e 4:2:2, 4:2:0).

– Image filtering/scaling.

• Configurable Filter Coefficients.

• Throughput of one sample per cycle for a 9-tap FIR filter.

• Can use the built-in accumulator to extend the FIR filter to more than 9-taps.

• Can be used for bilinear/bicubic interpolations.

– MPEG-4/H.264 Quarter Pixel Motion Compensation.

• Flexible input Pixel Selector.

– Can operate on numerous different image storage formats.

• Flexible Output Pixel Inserter.

– Scales and saturates the results back to 8-bit pixel values.

– Supports packed and planar output formats.

AT32AP7002 Datasheet(PDF) 13 Page - ATMEL Corporation

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