AT32AP7002 datasheet(53/896 Pages) ATMEL

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32054F–AVR32–09/09

AT32AP7002

PICOSVMAC – PICO Single Vector Multiplication and Accumulation

Description

Performs three vector multiplications where the input pixels taken from the INPIXn registers depends on the Input Selection

Mode and the input pixel addresses given in the instruction. The values in the VMUn_OUT registers are then accumulated

with the new results from the vector multiplications. The results from each Vector Multiplication Unit (VMU) are then added

together for one of the outputs to the Output Pixels Inserter to form the result of a single vector multiplication of two 9-ele-

ment vectors. The results from the VMUs are then scaled and saturated to unsigned 8-bit values before being inserted into

the OUTPIXn registers. Which pixels to update in the OUTPIXn registers depend upon the Output Insertion Mode and the

output pixel address given in the instruction.

Operation:

if ( Input Selection Mode == Horizontal Filter Mode ) then

else if ( Input Selection Mode == Vertical Filter Mode ) then

else if ( Input Selection Mode == Transformation Mode ) then

if ( Output Insertion Mode == Packed Insertion Mode ) then

OUT(d*3 + 0)

← SATSU(ASR(VMU0_OUT + VMU1_OUT + VMU2_OUT, COEFF_FRAC_BITS) , 8);

OUT(d*3 + 1)

← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);

OUT(d*3 + 2)

← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8);

else if ( Output Insertion Mode == Planar Insertion Mode ) then

OUT(d + 0)

← SATSU(ASR(VMU0_OUT + VMU1_OUT+ VMU2_OUT, COEFF_FRAC_BITS), 8);

OUT(d + 4)

← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);

OUT(d + 8)

← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8);

VMU0_OUT

COEFF0_0 COEFF0_1 COEFF0_2

IN(x+0)

IN(x+1)

IN(x+2)

VMU0_OUT

VMU1_OUT

COEFF1_0 COEFF1_1 COEFF1_2

IN(y+0)

IN(y+1)

IN(y+2)

VMU1_OUT

VMU2_OUT

COEFF2_0 COEFF2_1 COEFF2_2

IN(z+0)

IN(z+1)

IN(z+2)

VMU2_OUT

VMU0_OUT

COEFF0_0 COEFF0_1 COEFF0_2

IN((x+0)%11)

IN((x+4)%11)

IN((x+8)%11)

VMU0_OUT

VMU1_OUT

COEFF1_0 COEFF1_1 COEFF1_2

IN((y+0)%11)

IN((y+4)%11)

IN((y+8)%11)

VMU1_OUT

VMU2_OUT

COEFF2_0 COEFF2_1 COEFF2_2

IN((z+0)%11)

IN((z+4)%11)

IN((z+8)%11)

VMU2_OUT

VMU0_OUT

VMU1_OUT

VMU2_OUT

COEFF0_0 COEFF0_1 COEFF0_2

COEFF1_0 COEFF1_1 COEFF1_2

COEFF2_0 COEFF2_1 COEFF2_2

INx

INy

INz

VMU0_OUT

VMU1_OUT

VMU2_OUT

AT32AP7002 Datasheet(PDF) 53 Page - ATMEL Corporation

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