ATmega324P datasheet(171/377 Pages) ATMEL

171 / 377 page

171

7674F–AVR–09/09

ATmega164P/324P/644P

17. USART

17.1

Features

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

17.2

USART1 and USART0

The ATmega164P/324P/644P has two USART’s, USART0 and USART1.

The functionality for all USART’s is described below, most register and bit references in this sec-

tion are written in general form. A lower case “n” replaces the USART number.

USART0 and USART1 have different I/O registers as shown in “Register Summary” on page

356.

17.3

Overview

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a

highly flexible serial communication device.

A simplified block diagram of the USART Transmitter is shown in Figure 17-1 on page 172. CPU

accessible I/O Registers and I/O pins are shown in bold.

The Power Reducion USART0 bit, PRUSART0, in “PRR – Power Reduction Register” on page

47 must be disabled by writing a logical zero to it.

The Power Reducion USART1 bit, PRUSART1, in “PRR – Power Reduction Register” on page

47 must be disabled by writing a logical zero to it.

ATmega324P Datasheet(PDF) 171 Page - ATMEL Corporation