ATmega324P datasheet(175/377 Pages) ATMEL

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175

7674F–AVR–09/09

ATmega164P/324P/644P

17.4.3

External Clock

External clocking is used by the synchronous slave modes of operation. The description in this

section refers to Figure 17-2 on page 173 for details.

External clock input from the XCKn pin is sampled by a synchronization register to minimize the

chance of meta-stability. The output from the synchronization register must then pass through

an edge detector before it can be used by the Transmitter and Receiver. This process intro-

duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency

is limited by the following equation:

Note that f

osc depends on the stability of the system clock source. It is therefore recommended to

add some margin to avoid possible loss of data due to frequency variations.

17.4.4

Synchronous Clock Operation

When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input

(Slave) or clock output (Master). The dependency between the clock edges and data sampling

or data change is the same. The basic principle is that data input (on RxDn) is sampled at the

opposite XCKn clock edge of the edge the data output (TxDn) is changed.

Figure 17-3. Synchronous Mode XCKn Timing.

The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is

used for data change. As Figure 17-3 on page 175 shows, when UCPOLn is zero the data will

be changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data

will be changed at falling XCKn edge and sampled at rising XCKn edge.

fXCK

fOSC

-----------

RxD / TxD

XCK

RxD / TxD

XCK

UCPOL = 0

UCPOL = 1

Sample

ATmega324P Datasheet(PDF) 175 Page - ATMEL Corporation