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ATmega324P Datasheet(PDF) 274 Page - ATMEL Corporation |
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ATmega324P Datasheet(HTML) 274 Page - ATMEL Corporation |
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274 / 377 page  274 7674F–AVR–09/09 ATmega164P/324P/644P Figure 23-4. General Port Pin Schematic Diagram 23.5.2 Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 23-5 is inserted for the 5V reset signal. Figure 23-5. Observe-only Cell CLK RPx RRx WRx RDx WDx PUD SYNCHRONIZER WDx: WRITE DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN PUD: PULLUP DISABLE CLK : I/O CLOCK RDx: READ DDRx D L Q Q RESET RESET Q Q D Q Q D CLR PORTxn Q Q D CLR DDxn PINxn SLEEP SLEEP: SLEEP CONTROL Pxn I/O I/O See Boundary-scan Description for Details! PUExn OCxn ODxn IDxn PUExn: PULLUP ENABLE for pin Pxn OCxn: OUTPUT CONTROL for pin Pxn ODxn: OUTPUT DATA to pin Pxn IDxn: INPUT DATA from pin Pxn 0 1 DQ From Previous Cell ClockDR ShiftDR To Next Cell From System Pin To System Logic FF1 |
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