ATmega324P datasheet(324/377 Pages) ATMEL

324 / 377 page

324

7674F–AVR–09/09

ATmega164P/324P/644P

During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte

low and the high byte for each new Capture-DR state, starting with the low byte for the first Cap-

ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is

post-incremented after reading each high byte, including the first read byte. This ensures that

the first data is captured from the first address set up by PROG_COMMANDS, and reading the

last location in the page makes the program counter increment into the next page.

Figure 25-17. Flash Data Byte Register

The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal

operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate

through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis-

ter with sufficient number of clock pulses to complete its operation transparently for the user.

However, if too few bits are shifted between each Update-DR state during page load, the TAP

controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at

least 11 TCK cycles between each Update-DR state.

25.10.12 Programming Algorithm

All references below of type “1a”, “1b”, and so on, refer to Table 25-18 on page 320.

25.10.13 Entering Programming Mode

Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.

Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Program-

ming Enable Register.

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

STROBES

ADDRESS

State

Machine

ATmega324P Datasheet(PDF) 324 Page - ATMEL Corporation