ATmega324P datasheet(335/377 Pages) ATMEL

335 / 377 page

335

7674F–AVR–09/09

ATmega164P/324P/644P

Notes: 1. Values indicated represent typical data from design simulation.

2. Required only for fSCL > 100 kHz.

3. Cb = capacitance of one bus line in pF.

4. fCK = CPU clock frequency

5. This requirement applies to all ATmega164P/324P/644P Two-wire Serial Interface operation. Other devices connected to the

Two-wire Serial Bus need only obey the general fSCL requirement.

6. The actual low period generated by the ATmega164P/324P/644P Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK

must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7. The actual low period generated by the ATmega164P/324P/644P Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low

time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega164P/324P/644P devices con-

nected to the bus may communicate at full speed (400 kHz) with other ATmega164P/324P/644P devices, as well as any

other device with a proper tLOW acceptance margin.

Figure 26-5. 2-wire Serial Bus Timing

HIGH

High period of the SCL clock

fSCL ≤100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

SU;STA

Set-up time for a repeated START condition

SCL ≤100 kHz

4.7

–

µs

fSCL > 100 kHz

0.6

–

µs

tHD;DAT

Data hold time

SCL ≤100 kHz

3.45

µs

SCL > 100 kHz

0.9

µs

SU;DAT

Data setup time

fSCL ≤100 kHz

250

–

SCL > 100 kHz

100

–

SU;STO

Setup time for STOP condition

SCL ≤100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tBUF

Bus free time between a STOP and START

condition

SCL ≤100 kHz

4.7

–

µs

SCL > 100 kHz

1.3

–

µs

Table 26-7.

2-wire Serial Bus Requirements(1) (Continued)

Symbol

Parameter

Condition

Min

Max

Units

tSU;STA

tLOW

tHIGH

tLOW

tof

tHD;STA

tHD;DAT

tSU;DAT

tSU;STO

tBUF

SCL

SDA

ATmega324P Datasheet(PDF) 335 Page - ATMEL Corporation

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