ATmega88 datasheet(135/340 Pages) ATMEL

135 / 340 page

135

7530H–AVR–02/09

ATmega48/88/168 Automotive

Figure 15-1. 8-bit Timer/Counter Block Diagram

15.1.1

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg-

isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag

(TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from

the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by

the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock

source he Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-

tive when no clock source is selected. The output from the Clock Select logic is referred to as the

timer clock (clk

T2).

The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and

OC2B). See “Output Compare Unit” on page 137. for details. The compare match event will also

set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare

interrupt request.

Timer/Counter

OCRnA

OCRnB

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Fixed

TOP

Value

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

TCCRnA

TCCRnB

clk

Prescaler

T/C

Oscillator

clk

I/O

TOSC1

TOSC2

ATmega88 Datasheet(PDF) 135 Page - ATMEL Corporation

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