ATmega88 datasheet(214/340 Pages) ATMEL

214 / 340 page

214

7530H–AVR–02/09

ATmega48/88/168 Automotive

Figure 19-10. TWI Address Match Logic, Block Diagram

• Bit 0 – Res: Reserved Bit

This bit is an unused bit in the ATmega48/88/168, and will always read as zero.

19.7

Using the TWI

The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like

reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,

the application software is free to carry on other operations during a TWI byte transfer. Note that

the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in

SREG allow the application to decide whether or not assertion of the TWINT Flag should gener-

ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in

order to detect actions on the TWI bus.

When the TWINT Flag is asserted, the TWI has finished an operation and awaits application

response. In this case, the TWI Status Register (TWSR) contains a value indicating the current

state of the TWI bus. The application software can then decide how the TWI should behave in

the next TWI bus cycle by manipulating the TWCR and TWDR Registers.

Figure 19-11 is a simple example of how the application can interface to the TWI hardware. In

this example, a Master wishes to transmit a single data byte to a Slave. This description is quite

abstract, a more detailed explanation follows later in this section. A simple code example imple-

menting the desired behavior is also presented.

Address

Match

Address Bit Comparator 0

Address Bit Comparator 6..1

TWAR0

TWAMR0

Address

Bit 0

ATmega88 Datasheet(PDF) 214 Page - ATMEL Corporation