ATmega88 datasheet(260/340 Pages) ATMEL

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260

7530H–AVR–02/09

ATmega48/88/168 Automotive

Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an

LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set

in the SPMCSR, the value of the Extended Fuse byte will be loaded in the destination register as

shown below. See Table 25-5 on page 280 for detailed description and mapping of the Extended

Fuse byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

23.1.4

Preventing Flash Corruption

During periods of low V

CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating

voltage matches the detection level. If not, an external low V

CC reset protection circuit

can be used. If a reset occurs while a write operation is in progress, the write operation

will be completed provided that the power supply voltage is sufficient.

Keep the AVR core in Power-down sleep mode during periods of low V

CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

23.1.5

Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 24-5 shows the typical pro-

gramming time for Flash accesses from the CPU.

Bit

3210

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Table 23-1.

SPM Programming Time

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

ATmega88 Datasheet(PDF) 260 Page - ATMEL Corporation

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