ATmega88 datasheet(272/340 Pages) ATMEL

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7530H–AVR–02/09

ATmega48/88/168 Automotive

24.7.6

Prevent Reading the RWW Section During Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is always

blocked for reading. The user software itself must prevent that this section is addressed during

the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW

section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS

as described in “Watchdog Timer” on page 47, or the interrupts must be disabled. Before

addressing the RWW section after the programming is completed, the user software must clear

the RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader”

on page 274 for an example.

24.7.7

Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR

and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits

are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft-

ware update by the MCU.

See Table 24-2 and Table 24-3 for how the different settings of the Boot Loader bits affect the

Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an

SPM instruction is executed within four cycles after BLBSET and SELFPRGEN are set in

SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it is rec-

ommended to load the Z-pointer with 0x0001 (same as used for reading the lO

ck bits). For future

compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock

bits. When programming the Lock bits the entire Flash can be read during the operation.

24.7.8

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

24.7.9

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM

instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set

in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET

and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM

instruction is executed within three CPU cycles or no SPM instruction is executed within four

CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the

Instruction set Manual.

Bit

BLB12

BLB11

BLB02

BLB01

Bit

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

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