ATmega16U4 datasheet(313/408 Pages) ATMEL

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7766D–AVR–01/09

ATmega16U4/ATmega32U4

channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then

ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result

is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on

page 306.

24.9.4

ADC Control and Status Register B – ADCSRB

• Bit 7 – ADHSM: ADC High Speed Mode

Writing this bit to one enables the ADC High Speed mode. This mode enables higher conversion

rate at the expense of higher power consumption.

• Bit 5 – MUX5: Analog Channel Additional Selection Bits

This bit make part of MUX5:0 bits of ADRCSRB and ADMUX register, that select the combina-

tion of analog inputs connected to the ADC (including differential amplifier configuration).

• Bit 3:0 – ADTS3:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS3:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected interrupt flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[3:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set

Bit

432

ADHSM

ACME

MUX5

ADTS3

ADTS2

ADTS1

ADTS0

ADCSRB

Read/Write

R/W

Initial Value

Table 24-6.

ADC Auto Trigger Source Selections

ADTS3

ADTS2

ADTS1

ADTS0

Trigger Source

Free Running mode

Analog Comparator

External Interrupt Request 0

Timer/Counter0 Compare Match

Timer/Counter0 Overflow

Timer/Counter1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter1 Capture Event

Timer/Counter4 Overflow

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