ATmega16A datasheet(298/352 Pages) ATMEL

298 / 352 page

298

8154B–AVR–07/09

ATmega16A

Notes:

1. In ATmega16A, this parameter is characterized and not 100% tested.

2. Required only for f

SCL > 100 kHz.

3. Cb = capacitance of one bus line in pF.

4. fCK = CPU clock frequency

5. This requirement applies to all ATmega16A Two-wire Serial Interface operation. Other devices connected to the Two-wire

Serial Bus need only obey the general fSCL requirement.

6. The actual low period generated by the ATmega16A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than

6 MHz for the low time requirement to be strictly met at f

SCL = 100 kHz.

7. The actual low period generated by the ATmega16A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time require-

ment will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega16A devices connected to the bus may

communicate at full speed (400 kHz) with other ATmega16A devices, as well as any other device with a proper t

LOW accep-

tance margin.

Figure 27-4. Two-wire Serial Bus Timing

27.8

SPI Timing Characteristics

Figure 27-5. SPI Serial Programming Waveforms

tHD;DAT

Data hold time

SCL ≤ 100 kHz

3.45

µs

SCL > 100 kHz

0.9

µs

tSU;DAT

Data setup time

fSCL ≤ 100 kHz

250

–

SCL > 100 kHz

100

–

SU;STO

Setup time for STOP condition

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tBUF

Bus free time between a STOP and START

condition

SCL ≤ 100 kHz

4.7

–

µs

fSCL > 100 kHz

1.3

–

µs

Table 27-4.

Two-wire Serial Bus Requirements (Continued)

Symbol

Parameter

Condition

Min

Max

Units

tSU;STA

tLOW

tHIGH

tLOW

tof

tHD;STA

tHD;DAT

tSU;DAT

tSU;STO

tBUF

SCL

SDA

MSB

LSB

SERIAL CLOCK INPUT

(SCK)

SERIAL DATA INPUT

(MOSI)

(MISO)

SAMPLE

SERIAL DATA OUTPUT

ATmega16A Datasheet(PDF) 298 Page - ATMEL Corporation

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