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ATmega16A Datasheet(PDF) 299 Page - ATMEL Corporation |
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ATmega16A Datasheet(HTML) 299 Page - ATMEL Corporation |
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299 / 352 page ![]() 299 8154B–AVR–07/09 ATmega16A . Figure 27-6. SPI Interface Timing Requirements (Master Mode) Table 27-5. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 18-5 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • t SCK 7 SCK to out Master 10 8 SCK to out high Master 10 9SS low to out Slave 15 10 SCK period Slave 4 • tSCK 11 SCK high/low Slave 2 • tSCK 12 Rise/Fall time Slave 1.6 µs 13 Setup Slave 10 ns 14 Hold Slave 10 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 2 • tSCK MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 61 22 3 45 8 7 |
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