ATA8205 datasheet(21/46 Pages) ATMEL

21 / 46 page

9121B–INDCO–04/09

ATA8203/ATA8204/ATA8205

Figure 9-3.

Data Clock Disappears Because of a Logical Error

Figure 9-4.

Output of the Data Clock After a Successful Bit Check

The delay of the data clock is calculated as follows: t

Delay = tDelay1 + tDelay2

Delay1 is the delay between the internal signals Data_Out and Data_In. For the rising edge, tDelay1

depends on the capacitive load C

L at pin DATA and the external pull-up resistor Rpup. For the

falling edge, t

Delay1 depends additionally on the external voltage VX (see Figure 9-5, Figure 9-6

on page 22 and Figure 13-2 on page 30). When the level of Data_In is equal to the level of

Data_Out, the data clock is issued after an additional delay t

Delay2.

Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load at

pin DATA is exceeded, the data clock disappears (see Section 14. “Data Interface” on page 32).

Data_out (DATA)

DATA_CLK

Dem_out

'1'

'0'

'1'

'0'

'1'

'?'

Data

Receiving mode,

data clock control

logic active

Receiving mode,

bit check active

Logical error (Manchester code violation)

'0'

'1'

Data_out (DATA)

DATA_CLK

Dem_out

'1'

'0'

'1'

'0'

'1'

Data

Bit check ok

Start bit

Receiving mode,

data clock control

logic active

Receiving mode,

bit check active

'1'

ATA8205 Datasheet(PDF) 21 Page - ATMEL Corporation

ATA8205 Datasheet(HTML) 21 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL