SC195 datasheet(12/18 Pages) SEMTECH

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SC195

General Description

The SC195 is a synchronous step-down Pulse Width

Modulated (PWM) DC-DC regulator utilizing a 3.5MHz

fixed-frequency voltage mode architecture. The device is

designed to operate in fixed-frequency PWM mode and

enter power save (PSAVE) mode utilizing pulse frequency

modulation under light load conditions to maximize effi-

ciency. The device requires only two capacitors and a

single inductor to be implemented in most systems. The

switching frequency has been chosen to minimize the size

of the inductor and capacitors while maintaining high

efficiency. The output voltage is programmable, eliminat-

ing the need for external programming resistors. Loop

compensation is also internal, eliminating the need for

external components to control stability.

Programmable Output Voltage

The SC195 has fifteen fixed output voltage levels which

can be individually selected by programming the CTL

control pins (CTL1-CTL4 — see Table 1 on page 2 for set-

tings). The device is disabled whenever all four CTL pins

are pulled low and enabled whenever at least one of the

CTL pins is pulled high. This control approach eliminates

the need for a dedicated enable pin. Each CTL pin is inter-

nally pulled down via 1MΩ if V

is below 1.5V or if the

voltage on the control pin is below the input high voltage.

This ensures that the output is disabled when power is

applied if there are no inputs to the CTL pins. Each weak

pull-down is disabled whenever its pin is pulled high and

remains disabled until all CTL pins are pulled low.

The output voltage can be set using different approaches.

If a static output voltage is required, the CTL pins can be

tied to either IN or GND so that the desired voltage is set

whenever power is applied at IN. If enable control is

required, each CTL pin can be tied to either GND or to a

microprocessor I/O line to create the desired control code

whenever the control signal is forced high. This approach

is equivalent to using the CTL pins collectively as a single

enable pin. A third option is to connect each of the four

CTL pins to individual microprocessor I/O lines. Any of the

15 output voltages can be programmed using this

approach. If only two output voltages are needed, the

CTL pins can be combined in a way that will reduce the

number of I/O lines to 1, 2, or 3, depending on the control

code for each desired voltage. Other CTL pins could be

hard wired to GND or IN. This option allows dynamic

voltage adjustment for systems that reduce the supply

voltage when entering sleep states. Note that applying

all zeros to the CTL pins when changing the output volt-

ages will temporarily disable the device, so it is important

to avoid this combination when dynamically changing

levels.

PWM Operation

Normal PWM operation occurs when the output load

current exceeds the PSAVE threshold. In this mode, the

PMOS high side switch is activated with the duty cycle

required to produce the output voltage programmed by

the CTL pins. An internal synchronous NMOS rectifier

eliminates the need for an external Schottky diode on

the LX pin. As V

decreases, the duty cycle (percentage

of time PMOS is active) increases. As the input voltage

approaches the programmed output voltage, the duty

cycle approaches 100% (PMOS always on) and the device

enters a pass-through mode until the input voltage

increases or the load decreases enough to allow PWM

switching to resume.

Power Save Mode Operation

When the load current decreases below the PSAVE

threshold, PWM switching stops and the device auto-

matically enters PSAVE mode. This threshold varies

depending on the input voltage and output voltage

setting, optimizing efficiency for all possible load currents

- whether in PWM or PSAVE mode. While in PSAVE mode,

output voltage regulation is controlled by a series of

bursts in switching. During a burst, the inductor current

is limited to a peak value which controls the on-time of

the PMOS switch. After reaching this peak, the PMOS

switch is disabled and the inductor current is forced to

near 0mA. Switching bursts continue until the output

voltage climbs to V

OUT

+2.5% or until the PSAVE current

limit is reached. Switching is then stopped to eliminate

switching losses, enhancing overall efficiency. Switching

resumes when the output voltage reaches the lower

threshold of V

OUT

and continues until the upper threshold

again is reached. Note that the output voltage is regu-

lated hysteretically while in PSAVE mode between V

OUT

and V

OUT

+ 2.5%. The period and duty cycle while in PSAVE

mode are solely determined by V

and V

OUT

until PWM

Applications Information

SC195 Datasheet(PDF) 12 Page - Semtech Corporation

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