SC195 datasheet(16/18 Pages) SEMTECH

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SC195

calculating the minimum value required for C

from the

equation

ESR

OUT

The input capacitor RMS ripple current varies with the

input and output voltage. The maximum input capacitor

RMS current is found from the equation

OUT

RMS

The input voltage ripple and RMS current ripple are at

maximum levels when the input voltage is twice the

output voltage (50% duty cycle scenario).

The input capacitor provides a low impedance loop for

the edges of pulsed current drawn by the PMOS switch.

Low ESR/ESL X5R ceramic capacitors are recommended

for this function. To minimize stray inductance, the capaci-

tor should be placed as closely as possible to the IN and

GND pins of the SC195. Table 4 lists the recommended

input capacitor options from different manufacturers.

Table 4 — Recommended Input Capacitors

Manufacturer

Part Nunber

Value

(μF)

Type

Rated

Voltage

(VDC)

Dimensions

LxWxH (mm)

Case Size

Murata

GRM188R60J475K

4.7±10%

X5R

6.3

1.6x0.8x0.8

0603

Murata

GRM188R60J106K

10±10%

X5R

6.3

1.6x0.8x0.8

0603

Taiyo Yuden

JMK107BJ475KA

4.7±10%

X5R

6.3

1.6x0.8x0.8

0603

PCB Layout Considerations

The layout diagram in Figure 2 shows a recommended

PCB top-layer for the SC195 and supporting components.

Specified layout rules must be followed since the layout is

critical for achieving the performance specified in the

Electrical Characteristics table. Poor layout can degrade

the performance of the DC-DC converter and can contrib-

Applications Information (continued)

ute to EMI problems, ground bounce, and resistive voltage

losses. Poor regulation and instability can result.

The following guidelines are recommended for designing

a PCB layout:

The input capacitor, C

should be placed as close to the

VIN and GND pins as possible. This capacitor provides

a low impedance loop for the pulsed currents present

at the buck converter’s input. Use short wide traces

to connect as closely to the IC as possible. This will

minimize EMI and input voltage ripple by localizing

the high frequency current pulses.

Keep the LX pin traces as short as possible to minimize

pickup of high frequency switching edges to other

parts of the circuit. C

OUT

and L

should be connected

as close as possible between the LX and GND pins,

with a direct return to the GND.

Use a ground plane referenced to the GND pin. Use

several vias to connect to the component side ground

to further reduce noise and interference on sensitive

circuit nodes.

Route the output voltage feedback/sense path away

from the inductor and LX node to minimize noise and

magnetic interference.

Minimize the resistance from the OUT and GND pins

to the load. This will reduce errors in DC regulation

due to voltage drops in the traces.

CTL3

CTL2

CTL1

CTL0

CIN

COUT

SC195

4.8mm

3mm

Figure 2 — Recommended PCB Layout

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