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LTC6801 Datasheet(PDF) 3 Page - Linear Technology |
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LTC6801 Datasheet(HTML) 3 Page - Linear Technology |
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3 / 28 page  LTC6801 3 6801p ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 43.2V, V– = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Specifications VERR Measurement Error VCELL > 0.8V, 10V < V+ < 50V VCELL > 0.8V, 10V < V+ < 50V VCELL ≤ 0.8V, 10V < V+ < 50V VCELL ≤ 0.8V, 10V < V+ < 50V l l –0.5 –1 –1.5 –2 0.5 1 1.5 2 % % % % VCELL Cell Voltage Range Full Scale Voltage Range 5 V VCM Common Mode Voltage Range Measured Relative to V– VERR Specifications Met Range of Inputs Cn, n = 3 to 11 Range of Input C2 Range of Input C1 l l l 1.8 1.2 0 5 • n 10 5 V V V VOV Overvoltage (OV) Detection Level Programmed for 4.128V, Increasing VCELL, 10V < V+ < 50V l 4.079 4.120 4.161 V VUV Undervoltage (UV) Detection Level Programmed for 2.112V, Decreasing VCELL, 10V < V+ < 50V l 2.087 2.108 2.129 V VTV Temperature Input Detection Level Error (Relative to VREF/2) 10V < V+ < 50V l –18 12 mV HYS UV/OV Detection Hysteresis Error (Relative to Selected Value) 10V < V+ < 50V l –25 25 % VREF Reference Pin Voltage VREF Pin Loaded With 100k to V– l 3.043 3.038 3.058 3.058 3.073 3.078 V V Reference Voltage Temperature Coefficient 5 ppm/˚C Reference Voltage Hysteresis 50 ppm Reference Voltage Long Term Drift 60 ppm/√khr VREG Regulator Pin Voltage 10 < VS < 50, No Load 10 < VS < 50, ILOAD = 4mA l l 4.5 4.1 5 4.8 5.5 V V Regulator Pin Short Circuit Current Limit l 59 mA VS Supply Voltage, V+ Relative to V– VERR Specifications Met l 10 50 V IB Input Bias Current In/Out of Pins C1 Thru C12 When Measuring Cells During Self Test When Measuring Cells When Idle l –10 100 1 10 μA μA nA IM Supply Current, Monitor Mode Current Into the V+ Pin While Monitoring for UV and OV Conditions, FENA = 10kHz Continuous Monitoring Monitor Every 130ms Monitor Every 500ms l 500 700 200 90 1000 μA μA μA IQS Supply Current, Idle Current into the V+ Pin When Idle, FENA = 0 l 20 30 40 μA LTC6801 Timing Specifications TCYCLE Measurement Cycle Time DC = CC1 = CC0 = VREG l 13.5 15.5 17.5 ms FENA Valid EIN/EIN Frequency l 250 kHz TENA Valid EIN/EIN Period = 1/ FENA l 20 500 μs DCENA Valid EIN/EIN Duty Cycle FENA = 50kHz l 40 60 % LTC6801 Single Ended Digital I/O Specifications (SLT, SLTOK Pins) VIH Digital Input Voltage High SLT Pin l 2V VIL Digital Input Voltage Low SLT Pin l 0.5 V VODL Digital Output Voltage Low, Open Drain SLT Pin, 10k to VREG l 0.3 V VOH Digital Output Voltage High SLTOK Pin, 10k to V– l VREG– 0.3 V VOL Digital Output Voltage Low SLTOK Pin, 10k to VREG l 0.3 V |
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