MPC8548E datasheet(141/144 Pages) FREESCALE

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MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

Freescale Semiconductor

141

Document Revision History

23 Document Revision History

Table 84 provides a revision history for the MPC8548E hardware specification.

Table 84. Document Revision History

Revision

Date

Substantive Change(s)

12/2009

• In Section 5.1, “Power-On Ramp Rate” added explanation that Power-On Ramp Rate is required to

avoid falsely triggering ESD circuitry.

•In Table 10 changed required ramp rate from 545 V/s for MVREF and VDD/XVDD/SVDD to 3500 V/s

for MVREF and 4000 V/s for VDD.

•In Table 10 deleted ramp rate requirement for XVDD/SVDD.

•In Table 10 footnote 1 changed voltage range of concern from 0– 400 mV to 20 – 500mV.

•In Table 10 added footnote 2 explaining that VDD voltage ramp rate is intended to control ramp rate of

AVDD pins.

10/2009

• In Table 27, ”GMII Receive AC Timing Specifications,” changed duty cycle specification from 40/60 to

35/75 for RX_CLK duty cycle.

• Updated tMDKHDX in Table 37, “MII Management AC Timing Specifications.”

• Added a reference to Revision 2.1.2.

• Updated Table 55, “MII Management AC Timing Specifications.”

• Added Section 5.1, “Power-On Ramp Rate.”

04/2009

• In Table 1, “Absolute Maximum Ratings 1,” and in Table 2, “Recommended Operating Conditions,”

moved text, “MII management voltage” from LVDD/TVDD to OVDD, added “Ethernet management” to

OVDD row of input voltage section.

•In Table 5, “SYSCLK AC Timing Specifications,” added notes 7 and 8 to SYSCLK frequency and cycle

time.

•In Table 36, “MII Management DC Electrical Characteristics,” changed all instances of LVDD/OVDD to

OVDD.

• Modified Section 15, “High-Speed Serial Interfaces (HSSI),” to reflect that there is only one SerDes.

• Modified DDR clk rate min from 133 to 166 MHz.

• Modified note in Table 71, “Processor Core Clocking Specifications (MPC8548E and MPC8547E), “.”

•In Table 52, “Differential Transmitter (TX) Output Specifications,” modified equations in Comments

column, and changed all instances of “LO” to “L0.” In addition, added note 8.

•In Table 53, “Differential Receiver (RX) Input Specifications,” modified equations in Comments column,

and in note 3, changed “TRX-EYE-MEDIAN-to-MAX-JITTER,” to “TRX-EYE-MEDIAN-to-MAX-JITTER.”

• Modified Table 79, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”

• Added a note on Section 4.1, “System Clock Timing,” to limit the SYSCLK to 100 MHz if the core

frequency is less than 1200 MHz

•In Table 67, “MPC8548E Pinout ListingTable 68, “MPC8547E Pinout ListingTable 69, “MPC8545E

Pinout ListingTable 70, “MPC8543E Pinout Listing,” added note 5 to LA[28:31].

• Added note to Table 79, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”

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