MPC8548E datasheet(142/144 Pages) FREESCALE

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MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

142

Freescale Semiconductor

Document Revision History

01/2009

• [Section 4.6, “Platform Frequency Requirements for PCI-Express and Serial RapidIO.” Changed

minimum frequency equation to be 527 MHz for PCI x8.

•In Table 5, added note 7.

• Section 4.5, “Platform to FIFO Restrictions.” Changed platform clock frequency to 4.2.

• Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics.” Added MII after GMII

and add ‘or 2.5 V’ after 3.3 V.

•In Table 23, modified table title to include GMII, MII, RMII, and TBI.

•In Table 24 and Table 25, changed clock period minimum to 5.3.

•In Table 25, added a note.

•In Table 26, Table 27, Table 28, Table 29, and Table 30, removed subtitle from table title.

•In Table 30 and Figure 15, changed all instances of PMA to TSEC

•In Section 8.2.5, “TBI Single-Clock Mode AC Specifications.” Replaced first paragraph.

•In Table 34, Table 35, Figure 18, and Figure 20, changed all instances of REF_CLK to

TSEC

n_TX_CLK.

•In Table 36, changed all instances of OVDD to LVDD/TVDD.

•In Table 37, “MII Management AC Timing Specifications,” changed MDC minimum clock pulse width

high from 32 to 48 ns.

• Added new section, Section 15, “High-Speed Serial Interfaces (HSSI).”

• Section 16.1, “DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK.” Added new

paragraph.

• Section 17.1, “DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK.” Added new

paragraph.

• Added information to Figure 63, both in figure and in note.

• Section 21.3, “Decoupling Recommendations.” Modified the recommendation.

• Table 83, “Part Numbering Nomenclature.” In Silicon Version column added Ver. 2.1.2.

04/2008

• Removed 1:1 support on Table 78, “e500 Core to CCB Clock Ratio.”

• Removed MDM from Table 18, “DDR SDRAM Input AC Timing Specifications.” MDM is an Output.

• Figure 56, “PLL Power Supply Filter Circuit with PLAT Pins” (AVDD_PLAT).

• Figure 57, “PLL Power Supply Filter Circuit with CORE Pins” (AVDD_CORE).

•Split Figure 58, “PLL Power Supply Filter Circuit with PCI/LBIU Pins,” (formerly called just “PLL Power

Supply Filter Circuit”) into three figures: the original (now specific for AVDD_PCI/AVDD_LBIU) and two

new ones.

Table 84. Document Revision History (continued)

Revision

Date

Substantive Change(s)

MPC8548E Datasheet(PDF) 142 Page - Freescale Semiconductor, Inc

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