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ST7575 Datasheet(PDF) 22 Page - Sitronix Technology Co., Ltd. |
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ST7575 Datasheet(HTML) 22 Page - Sitronix Technology Co., Ltd. |
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22 / 51 page  ST7575 Ver 1.3 22/51 2007/09/12 Column Address Circuit Column Address Circuit has an 8-bit preset counter that provides Column Address to the DDRAM. The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. TMX and TMY make it possible to invert the relationship between the addresses (Line Address and Column Address) and the outputs (COM/SEG). It is necessary to rewrite the display data into built-in RAM after changing TMX setting. The relation between DDRAM and outputs with different TMX or TMY setting is shown below. B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 00H 01H 02H 03H 04H 05H 06H 07H Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 Page 9 ICON (COMS1, COMS2) PAD No. (SEG) D0 D1 D2 D3 Page Address Data TMX=0 Column Address (Hex) TMX=1 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 41H 40H 1/66 Duty COM Output Map 0 0 0 0 D0 D1 D2 D3 D4 D5 D6 D7 0 0 0 1 D0 D1 D2 D3 D4 D5 D6 D7 0 0 1 0 D0 D1 D2 D3 D4 D5 D6 D7 0 0 1 1 D0 D1 D2 D3 D4 D5 D6 D7 0 1 0 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 0 1 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 D0 D1 D2 D3 D4 D5 D6 D7 1 0 0 0 1 0 0 1 D7 D7 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 TMY=0 TMY=1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 PAD No. (COM) 248 247 246 245 244 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 157 158 159 160 161 162 163 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130, 243 Fig 8. Relationship between DDRAM and Outputs (COM/SEG) |
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