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ST7732 Datasheet(PDF) 59 Page - Sitronix Technology Co., Ltd. |
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ST7732 Datasheet(HTML) 59 Page - Sitronix Technology Co., Ltd. |
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59 / 168 page ![]() ST7732 Ver 1.5.2 2007-12 59 Table 9.9.6.3 Vertical and Horizontal Timing for RGB I/F Specification Item Symbol Condition Min Type. Max Unit Vertical Timing Vertical cycle period TVP GM=”00”&”01” 163 164 HS Vertical low pulse width TVS 1 4 HS Vertical front porch TVFP 1 1 512 HS Vertical back porch TVBP 1 512 HS Vertical data start line TVS + TVBP 2 3 512 HS Vertical blanking period TVBL TVS + TVBP + TVFP 3 4 512 HS Vertical active area TVDISP GM=”00”&”01” 160 HS Vertical refresh rate TVRR Frame rate 61.75 65 68.25 Hz Horizontal Timing GM=”00” 131 511 PCLK Horizontal cycle period THP GM=”01” 123 511 PCLK Horizontal low pulse width THS 1 63 PCLK Horizontal front porch THFP 1 63 PCLK Horizontal back porch THBP 1 63 PCLK Horizontal data start point THS + THBP 1 10 63 PCLK Horizontal blanking period THBL 3 20 256 PCLK GM=”00” 128 PCLK Horizontal active area THDISP GM=”01” 120 PCLK TPCLKCYC 100 634 720 ns fPCLKCYC 1.39 1.58 10 MHz TPCLKCYC 100 670 767 ns fPCLKCYC 1.30 1.49 10 MHz TPCLKCYC 100 788 896 ns Pixel clock cycle fPCLKCYC 1.12 1.27 10 MHz Note 1. VDDI=1.6 to 3.3V, VDD=2.5V to 3.3V, AGND=DGND=0V, Ta=-30 to 70℃ Note 2. Data lines can be set to “High” or “Low” during blanking time – Don’t care. Note 3. HP is multiples of eight PCLK. |
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