ACE5372

Low Power Real-Time Clock (RTC)

VER 1.2

6

Minute digit register ( at internal address 1H )

D7

D6

D5

D4

D3

D2

D1

D0

Operation

-

M40

M20

M10

M8

M4

M2

M1

Write

0

M40

M20

M10

M8

M4

M2

M1

Read

0

Undefined Undefined Undefined Undefined Undefined Undefined Undefined

Default

Hour digit register ( at internal address 2H)

D7 D6

D5

D4

D3

D2

D1

D0

Operation

-

-

H20 or P/

⎯A

H10

H8

H4

H2

H1

Write

0

0

H20 or P/

⎯A

H10

H8

H4

H2

H1

Read

0

0

Undefined

Undefined Undefined Undefined Undefined Undefined

Default

* Default means read value when XSTP bit is set to “I” by starting up from 0V, or supply voltage drop etc.

2. Day-of-the-week Counter ( at internal address 3H)

*Day-of-the-week digits are incremented by 1 when carried to 1-day digits.

*Day-of-the-week digits display (incremented in septimal notation):

(W4,W2,W1) = (0,0,0)→(0,0,1)→……→(1,1,0)→(0,0,0)

*The relation between days of the week and day-of-the-week digits is defined as:

Sunday=(0,0,0); Monday=(0,0,1); …… ; Saturday=(1,1,0)

(W4, W2, W1) should not be set to (1,1,1).

D7 D6 D5 D4 D3

D2

D1

D0

Operation

-

-

-

-

-

W4

W2

W1

Write

0

0

0

0

0

W4

W2

W1

Read

0

0

0

0

0

Undefined Undefined Undefined

Default

*The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc.

3. Calendar Counter ( at internal address4-6H )

the leap year.

Day digits: Range from 1 to 31 (for January, March, May, July, August, October, and December).

Range from 1 to 30 (for April, June, September, and November)

Range from 1 to 29 (for February in leap years)

Range from 1 to 28 (for February in ordinary years)

Month DIGITS:

Range from 1 to 12 and carried to year digits when cycled to 1. Carried to year digits when cycled from 12 to 1.

Year digits:

Range from 00 to 99 and 00,04,08, …….,92, and 96 are counted as leap years.

Any registered imaginary time should be replaced with correct time as carrying to such registered imaginary

time digits from lower-order ones cause the clock counter malfunction.