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AS8202NF TTP-C2NF

Asynchronous READYB permits the shortest possible bus cycle but eventually requires signal synchronization in the

Synchronous READYB uses an external clock (usually the host processor’s bus clock) for synchronization of the

host processor's bus clock to enable this mode of operation.

Note: Due to possible metastability occurrence, it is not recommended to be used in safety critical systems.

OEB

In

1

CNI output enable, active low

READYB

out (open drain)

1

CNI ready, active low

INTB

out (open drain)

1

CNI interrupt, time signal, active low

RAM_CLK_TESTSE

in

1

HOST clock

USE_RAM_CLK

in

1

HOST clock pin enable

Table 6. Asynchronous DPRAM interface

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Tc

Controller Cycle Time

25

ns

1a

Input Valid to CEB, WEB

(Setup Time)

A[11:0]

5ns

2a

D[15:0]

1b

CEB, WEB to Input Invalid

(Hold Time)

A[11:0]

3

ns

2b

D[15:0]

4

3

Input Rising to CEB, WEB

Falling

CEB, WEB, OEB

5

1

ns

4

CEB, WEB Rising to Input

Falling

CEB, WEB, OEB

5

1,2

ns

5

Write Access Time (CEB,

WEB to READYB)

min = 1 Tc, max = 4 Tc

25

100

ns

6

CEB, WEB de-asserted to

READYB de-asserted

9.4

ns

7a

Input Valid to CEB, OEB

(Setup Time)

A[11:0]

5

ns

7b

CEB, OEB to Input Invalid

(Hold Time)

A[11:0]

2

ns

8

Input Rising to CEB, OEB

Falling

CEB, WEB, OEB

5

1

ns

9

CEB, OEB Rising to Input

Falling

CEB, WEB, OEB

5

1

ns

10

Read Access Time (CEB,

OEB to READYB)

min = 1.5 Tc, max = 8 Tc

37.5

200

ns

11a

CEB, OEB asserted to

signal asserted

D[15:0]

4.0

8.4

ns

11b

CEB, OEB de-asserted to

signal de-asserted

D[15:0]

3.8

8

ns

11c

READYB

8.8

12

READYB, D skew

±2

ns

13

RAM_CLK_TESTSE

Rising to READYB Falling

USE_RAM_CLK=1

3.7

13.5

ns

Table 5. Host Interface Ports

Pin Name

Mode

Width

Comment